Superscalar pipeline design pdf

Aneel Kumar Raju Thirumalaraju. Md Mustafa raza. Alex Ordaz. Sergiu Ene. Munazza Fatma. Shivam Vyas. Entertainment official's. Zana Jarallah. Myat Thu Maung. Nz Saad. Hariharan Shankar. Dedi Irwanto. Hanuman Sai Majeti. Kaushik Karthikeyan K. Vhdl Implementation of a Mips Pipeline Processor. Yuvaraj D. Popular in Parallel Computing. Daniel Oktavianus. Shakya Gaurav. Vimmi Golu. Sanjay Nayak. Fardian Godang Majo Lelo. Mubeena Hamid. Kyler Greenway. Kaushik Hazarika. Raniere Slovich. International Journal of Linguistics and Computational Applications.

Nikhil Phul. Bhavini Kumawat. Bala Murugan. Jatin Baheliya. Fahad Mahmood. Jagadeeh Valasapalli. Umisha Shah. However, some of the units were further whole CPU design team met several times each week to broken down into multiple modules. PC update by incrementing changes, if any, to be made to the specifications. The team PC or from Branch Prediction Unit, instruction fetching from leader monitored the changes to make sure that these changes Instruction Cache, Instruction Receive and Decode Unit, and did not adversely affect the overall design.

Each module G. Testing the Low-Level Functionality in the pipeline design was assigned to an individual. The To reduce the extent of overall testing, we used an incremen- functional specification of each stage were clearly laid out. The tal testing approach. Each stage was built and tested thoroughly interface between all pairs of interacting stages neighbors in before it was integrated with other stages. Furthermore, inter- the pipeline were clearly defined including the signal names face tests were designed and testing was also performed after and naming conventions.

The meaning of each interface signal combining two neighboring stages to ensure that all designs and the signal conventions i. This allowed us to isolate any trigger or synchronous clock latch were also defined.

Then potential design flaws in individual modules and to fix the the design team along with the project coordinator estimated problems quickly. It should be noted that there were many the time it would take to design each module. This along with such flaws detected and fixed before testing the whole system. Integrating Individual Modules F. Building Individual Modules Once all the module design and testing was completed and Each member was given complete freedom in performing the interface testing was completed between individual pairs, his design.

The only obvious restriction was that all interface we began to put the whole processor unit together. To our surprise, it decided to promote it to the next level on March 2nd, did not take us long to get the whole processor working. We found that version control provided a lot of help to the design process. It was particularly useful for isolating the I. Testing Overall Functionality design flaws as well as facilitating repetitive testing.

Com- Once the CPU integration was completed, we began overall bining version control and incremental testing, we estimate testing of the CPU. If development time. After fixing all the In addition to the structured design approach and the version known bugs, we ran a test program on our machine as well control used in project management as described above, other as on some other simulated processors to do a benchmark design and work concepts were also employed including en- comparison.

For the bugs found during the benchmarking forcing coding and documentation standards, allowing flexible process, we repeated the same process of fixing them.

Documentation The final stage of the design process was to organize and A. Coding and Documentation Standards generate documentation for the processor. The documentation Adapting coding and documentation standards provided a includes the following.

It facilitated the design, because the functions and features of 2 Detailed design specifications for each stage and each each module were clearly defined and gave the project a neat unit.

Flexible Work Hours 5 Test programs and scripts that we used. One of the valuable contributions to the project from our the Co-Op experience of the design team members was adopting III. Flexible working In this project, we used the concepts of version control to hours not only made project scheduling simpler, but also gave streamline the design process. Version control is a concept the team members a sense of trust which motivated them to that employs a systematic way to keep track of the project work harder.

The down side to this approach was that the team development history. It allows easy reference to any level in leader had to keep track of the progress of each member, a the project development, and provides a good way to isolate very time-consuming task. Version control can be used or implemented in many dif- C.

Release Day ferent ways. In this project, we chose to implement version The other concept that we found very useful in a time control using the time stamps method. The team was only allowed to change the archi- time stamps attached to the filename. After 2 Time stamps included only month and day in. All stamp attached to its filename. This could be modified at any time by anyone. One problem we found in the design of a modern computer 6 Files were promoted to a new version when a particular was that there are many ways to do one thing.

Thus constant goal was achieved. To promote a file, we would copy the changes can be made to improve the design. These changes most current file to a file with the present day attached to are good in general but they are definitely bad for a time- the filename as a time stamp.

All the current test scripts constrained project. Changes tend to throw the project off were changed to reflect these changes. For example, if schedule. However, it also made the final design somewhat less comprehensive due to time constraints.

Our CPU included the following specific architectural features: 1 Superscalar architecture, which allowed two independent instructions to be executed simultaneously. Instruction format: Basic MIPS instruction format and format for the 2 Superpipeline architecture that consisted of nine pipeline second word in the extended instruction set.

After generating the instruction set, we were able to generate 4 Data Cache, which supported multiple accesses. Each of these advanced architectural features required a VI. Each building block is standing of modern microprocessor architecture. The material roughly a stage in the pipeline or some sort of control unit.

Please units for the processor. Instruction Set to hold two instructions coming from the instruction cache In this section, we discuss the chosen instruction set for the every clock cycle, a word instruction queue which gets processor. An instruction set provides a complete description the accepted instructions from the two-word buffer, and a of the capabilities of the processor. It is the first thing a b instruction buffer which provides four instructions to design team has to define.

A good instruction set should the dispatch unit every clock cycle. It is superpipelined into provide programmers all operations readily available in one the following three stages. With that in mind, we have designed for instruction fetch from memory. It sends the PC to the our enhanced instruction set. MIPS R as a model. To enhance the instruction cache. It then decodes the instructions and versatility of the instruction set, we added an additional type: extracts the relevant information and separates b and the E-type, for extended instructions.

This type of instruction b instructions. This step is necessary because our is just an extension of the R-type with the additional capability processors supports multiword instructions. The decoded of direct access memory for one of the operands. The E- instructions are stored on a word instruction queue.

This unit is called the instruction of an instruction or one of the two source operands. The other prefetch unit IPF. It feeds the dispatch unit with four source operand is always in a register in E-type instruction. They are extended The instruction fetch unit runs independently from the CPU to 64 b.

Create your free account to read unlimited documents. The SlideShare family just got bigger. Home Explore Login Signup. Successfully reported this slideshow. We use your LinkedIn profile and activity data to personalize ads and to show you more relevant ads. You can change your ad preferences anytime. Next SlideShares. You are reading a preview. Create your free account to continue reading. Sign Up. Upcoming SlideShare. Performance Enhancement with Pipelining. Embed Size px. Start on.

Show related SlideShares at end. WordPress Shortcode. Share Email.